1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits and, in particular, to a process for forming electrical isolation components of an integrated circuit.
2. Description of the Related Art
As semiconductor integrated circuit fabrication technology advances into the realm of very large scale integration (VLSI), new techniques must be developed to eliminate process deficiencies which were acceptable for devices having less dense configurations.
One area of concern is that of electrical isolation; i.e., the separation of individual active regions in the major surface of the semiconductor substrate and superposing structures by an insulator or dielectric component which will prevent undesirable electrical interaction.
A common technique for obtaining electrical isolation between adjacent active regions in an integrated circuit structure is the use of silicon dioxide regions, commonly referred to as "field oxide," or "isolation oxide," depending upon the exact usage in the integrated circuit structure. This fabrication process is commonly referred to as LOCOS--local oxidation of silicon. In metal-oxide-semiconductor (MOS) field effect transistor (FET) based devices, electrical isolation barrier regions formed in the substrate below a field oxide are also referred to as "channel stop" regions.
The LOCOS process is based on the fact that silicon nitride ("nitride") can be used as a mask against thermal oxidation of silicon because its oxidation rate is about 30 times slower than silicon. Additionally, silicon nitride can be selectively etched.
In such a process, isolation oxide is typically grown to a thickness such that the top of the oxide and the silicon substrate surface are in the same plane to minimize surface topography. U.S. Pat. No. 3,970,486 (Kooi) describes a LOCOS method for forming discrete oxide regions in a semiconductor surface.
However, as shown in FIG. 1, at the periphery of the active silicon areas, "bird's beaks" (resulting from lateral oxidation under masking materials) and "bird's crests" or "heads" (vertical rising at the corners of the etched silicon) are formed when nitride masking is used. These effects are not desirable. A bird's beak takes up lateral space. A bird's head produces greater surface topography, adding step coverage requirements for subsequently formed layers such as metal interconnections. Neither effect is acceptable in VSLI technology. In particular, long bird's beaks are clearly counterproductive to device shrinkage.
A second problem exists because of the extremely poor thermal expansion coefficient match between silicon nitride masks and the underlying silicon. One result is the formation of dislocations in the crystalline structure of unoxidized silicon regions. Such dislocations can cause junction leakages.
Yet another problem with nitride processes is called "white ribbon" or "browning." During the relatively high temperature cycles required, ammonia-nitride compounds are formed at silicon interfaces with the nitride. During subsequent fabrication steps, these tend to form voids in the structure which can cause, for example, electrical shorts at FET gate regions. Wet chemical cleaning or wet thermal oxidation processing, or both, are required to remove these compounds.
Hence, there is a need for a simple approach to forming electrical isolation components during integrated circuit fabrication to reduce or eliminate the problems in the prior art without inheriting process complexities.
Although the present invention is useful for many integrated circuit technologies, it is particularly advantageous for high density, high performance static random access memory (SRAM) device construction because of the very tight spacing and the narrow transistor width effect requirements.